DOI: 10.5593/sgem2017/21/S07.037


A. Antonov, P. Kustarev
Wednesday 13 September 2017 by Libadmin2017

References: 17th International Multidisciplinary Scientific GeoConference SGEM 2017, www.sgem.org, SGEM2017 Conference Proceedings, ISBN 978-619-7408-01-0 / ISSN 1314-2704, 29 June - 5 July, 2017, Vol. 17, Issue 21, 287-294 pp, DOI: 10.5593/sgem2017/21/S07.037


Raising abstraction level of designing of custom digital circuits is a major scientific and practical problem that attracts a lot of academic and industrial efforts nowadays. However, existing approaches to handling of this problem typically do not provide sufficient means of defining individual domain- and project-specific custom-level microarchitectural decisions being directed by custom user specification that coordinates their application via specialized controls embedded in this specification.
In the article, we introduce the concept of Language Intellectual Property (LIP) core. LIP core interfaces with a designer via a set of specialized language constructs that operate within certain microarchitectural pattern being used while leaving possibility of implementation of fully custom functionality, and narrow-domain-specific synthesizer that converts input LIP specification into standard specification or other LIPs. In terms of configurability, LIPs lay between traditional cores, that use configuration means of design languages being used, and fully custom standalone language with its own fully specific grammar and complete compiler infrastructure. Also, we describe the developed CAD framework, which offers practical implementation of LIP concept. We have developed LIP that implements pipeline pattern and applied it to the design of an educational pipelined processor core with DLX architecture. We evaluate the expressiveness of the proposed design constructions and common pitfalls that arise when complex control-intensive structures are designed using the developed toolset. Finally, we cover perspectives of future extending of the toolset’s capabilities with the focus on introduction of new design abstractions and constructs.

Keywords: SoC, microarchitecture, CAD, language IP core, domain-specific language

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